Programmable units presently used (DFPs, FPGAs—Field Programmable Gate Arrays) can be programmed in two different ways:                one-time only, i.e., the configuration can no longer be changed after programming. All configured elements of the unit perform the same function over the entire period during which the application takes place.        on site, i.e., the configuration can be changed after the unit has been installed by loading a configuration file when the application is started. Most units (in particular FPGA units) cannot be reconfigured during operation. For reconfigurable units, data usually cannot be further processed while the unit is being reconfigured, and the time required is very long.        
Configuration data is loaded into programmable units through a hardware interface. This process is slow and usually requires hundreds of milliseconds due to the limited band width accessing the external memory where the configuration data is stored, after which the programmable unit is available for the desired/programmed function as described in the configuration file.
A configuration is obtained by entering a special bit pattern of any desired length into the configurable elements of the unit. Configurable elements can be any type of RAM cells, multiplexers, interconnecting elements or ALUs. A configuration string is stored in such an element, so that the element preserves its configuration determined by the configuration string during the period of operation.
The existing methods and options present a series of problems, such as:                If a configuration in a DFP (see German Patent No. DE 44 16 881 A1) or an FPGA is to be modified, a complete configuration file must always be transmitted to the unit to be programmed, even if only a very small part of the configuration is to be modified.        As a new configuration is being loaded, the unit can only continue to process data to a limited extent or not at all.        With the increasing number of configurable elements in each unit (in particular in FPGA units), the configuration files of these units also become increasingly large (several hundred Kbytes on average). Therefore it takes a very long time to configure a large unit and often makes it impossible to do it during operation or affects the function of the unit.        When a unit is partially configured during operation, a central logic entity is always used, through which all reconfigurations are managed. This requires considerable communication and synchronization resources.        